This invention relates to a data demodulation apparatus and method, and more particularly to a data demodulation apparatus and method which uses a Viterbi decoding process to discriminate the data rate of receive data at a high speed.
A data rate communication method called blind transport format detection is known as one of data rate discrimination methods for a communication system in which a plurality of data rates are used.
According to the blind transport format detection, the data rate is discriminated in the following manner.
In particular, a data demodulation apparatus in a communication system in which a plurality of data rates are used cannot recognize the data rate at a point of time at which it receives data. More particularly, the number of possible data rates is prescribed in advance, and therefore, the data demodulation apparatus recognizes such possible data rates, but cannot recognize which one of the data rates is actually used by the receive data. Therefore, the data demodulation apparatus Viterbi decodes the received data and determines a maximum path metric value, a minimum path metric value and a zero-state path metric value for each data of the end bit position nend which may possibly be the end of an amount of data corresponding to the data rate as counted from the top of the receive data. Then, the data demodulation apparatus calculates the S value (a value represented by a function S(nend)) given by the following expression (1):S(nend)=10 log(((a0(nend)−amin(nend))/((amax(nend)−amin(nend)))  (1)where amax(nend) is the maximum path metric value at the end bit nend, amin(nend) is the minimum path metric value at the end bit nend, and a0(nend) is the zero-state path metric value at the end bit nend.
If the possible end bit is a true end bit, then the zero-state path metric value a0 (nend) exhibits a sufficiently low value, and therefore, the S value given by the expression (1) above has a sufficiently small value (a high value in the negative direction). On the other hand, if the possible end bit is not a true end bit, then the zero-state path metric value a0(nend) cannot assume a sufficiently low value, and therefore, the S value does not have a small value.
Thus, making use of the relationship just described, the S value calculated with regard to a predetermined end bit nend is compared with a predetermined threshold value D. Then, if the relationship given by the following expression (2) is not satisfied, then it is discriminated that the end bit nend is not a true end bit, and the S value of another end bit is determined.S(nend)≦D  (2)where the initial value of the threshold value D is set to a comparatively high value.
On the other hand, if the S value satisfies the expression (2) above, then the data demodulation apparatus executes a CRC (Cyclic Redundancy Check) check from the zero-state path memory data. If the CRC check does not reveal an error, then the data demodulation apparatus sets the S value at the end at the point of time to the threshold value D. This operation is repeated until the end bit nend that has the lowest S value (that is, the data length from the top data to the end bit nend) is finally detected as the data rate.
It is assumed that the data demodulation apparatus receives, for example, such receive data as seen in FIG. 1. The receive data of FIG. 1 includes a variable length data part (Data with variable number of bits) 1, a CRC part (CRC) 2, and an empty data part (Empty) 3.
If it is assumed that end bits E1 to E4 may possibly be an end bit nend as seen in FIG. 1, that is, if it is assumed that four data rates from the top (left end in FIG. 1) of the receive data to the end bits E1, E2, E3 and E4 are set in advance, then the data demodulation apparatus determines the S value with regard to each of the end bits E1 to E4 and repetitively compares the S values with the threshold value as described above. In the receive data of FIG. 1, the end bit E3 forms a break of the CRC part and makes a true end bit. Accordingly, the S value exhibits a minimum value at the end bit E3, and as a result, the data length from the top to the end bit E3 of the received data is discriminated as the data rate.
In the blind transport format detection described above, the arithmetic operation of the maximum path metric value amax(nend), minimum path metric value amin(nend) and zero-state path metric value a0(nend) with regard to each possible end bit involves repetitions of a Viterbi decoding process from the top bit to all end bits which each may possibly be a true end bit.
In particular, for example, referring to FIG. 2, in order to determine the maximum path metric value amax(E1), minimum path metric value amin(E1) and zero-state path metric value a0(E1) with regard to the end bit E1 in the top stage in FIG. 2, the Viterbi decoding process is performed for each of the bits from the top bit 0 to the end bit E1 in the top stage in FIG. 2.
Meanwhile, in order to determine the maximum path metric value amax(E2), minimum path metric value amin(E2) and zero-state path metric value a0(E2) with regard to the end bit E2 in the second top stage in FIG. 2, the Viterbi decoding process is performed for each of the bits from the top bit 0 to the end bit E2 in the second top stage in FIG. 2.
If n bit rates are set in advance as seen in FIG. 2, such a Viterbi decoding process as described above is repeated to determine the maximum path metric value amax(En), minimum path metric value amin(En) and zero-state path metric value a0(En) with regard to each of the end bits E1 to En, and the S values determined based on the thus determined path metric values are compared and the data length from the top bit to the end bit En corresponding to Smin is discriminated as the bit rate.
However, if the Viterbi decoding process is executed in accordance with the procedure described above to perform bit rate discrimination, then since a similar Viterbi decoding process must be repeated by a number of times equal to the number of possible end bits, that is, the set number of data rates, much time is required for arithmetic operation to finally detect a true end bit. As a result, the technique described above has a subject to be solved in that much time is required for discrimination of the bit rate.
In order to overcome the subject just described, it is a possible idea to use a plurality of Viterbi decoders such that the above-described Viterbi decoding process is executed parallelly thereby to perform the necessary arithmetic operation at an increased speed. This, however, results in another subject that the apparatus scale is increased and also the cost is increased.